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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
GTX Transceiver Protocol Jitter Characteristics
For Table 61 through Table 66 , the 7 Series FPGAs GTX/GTH Transceivers User Guide ( UG476 ) contains recommended
settings for optimal usage of protocol specific characteristics.
Table 61: Gigabit Ethernet Protocol Characteristics
Description
Line Rate (Mb/s)
Min
Max
Units
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
1250
–
0.24
UI
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
1250
0.749
–
UI
Table 62: XAUI Protocol Characteristics
Description
Line Rate (Mb/s)
Min
Max
Units
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ)
3125
–
0.35
UI
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
3125
0.65
–
UI
Table 63: PCI Express Protocol Characteristics (1)
Standard
Description
Line Rate (Mb/s)
Min
Max
Units
PCI Express Transmitter Jitter Generation
PCI Express Gen 1
PCI Express Gen 2
PCI Express Gen 3 (2)
Total transmitter jitter
Total transmitter jitter
Total transmitter jitter uncorrelated
Deterministic transmitter jitter uncorrelated
2500
5000
8000
–
–
–
–
0.25
0.25
31.25
12
UI
UI
ps
ps
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1
PCI Express Gen 2 (3)
Total receiver jitter tolerance
Receiver inherent timing error
Receiver inherent deterministic timing error
0.03 MHz–1.0 MHz
2500
5000
0.65
0.40
0.30
1.00
–
–
–
–
UI
UI
UI
UI
PCI Express Gen
3 (2)
Receiver sinusoidal jitter
tolerance
1.0 MHz–10 MHz
8000
Note 4
–
UI
10 MHz–100 MHz
0.10
–
UI
Notes:
1.
2.
3.
4.
Tested per card electromechanical (CEM) methodology.
PCI-SIG 3.0 certification and compliance test boards are currently not available.
Using common REFCLK.
Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade.
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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